Field
The field relates to direct wafer bonding, and more particularly to the bonding and electrical interconnection of substrates to be utilized in semiconductor device and integrated circuit fabrication.
Description of the Related Art
As the physical limits of conventional CMOS device are being approached and the demands for high performance electronic systems are imminent, system-on-a chip (SOC) is becoming a natural solution of the semiconductor industry. For system-on-a chip preparation, a variety of functions are required on a chip. While silicon technology is the mainstay technology for processing a large number devices, many of the desired circuit and optoelectronic functions can now best be obtained from individual devices and/or circuits fabricated in materials other than silicon. Hence, hybrid systems which integrate non-silicon based devices with silicon based devices offer the potential to provide unique SOC functions not available from pure silicon or pure non-silicon devices alone.
One method for heterogeneous device integration has been the hetero-epitaxial growth of dissimilar materials on silicon. To date, such hetero-epitaxial growth has realized a high density of defects in the hetero-epitaxial grown films, largely due to the mismatches in lattice constants between the non-silicon films and the substrate.
Another approach to heterogeneous device integration has been wafer bonding technology. However, wafer bonding of dissimilar materials having different thermal expansion coefficients at elevated temperature introduces thermal stresses that lead to dislocation generation, debonding, or cracking. Thus, low temperature bonding is desired. Low temperature bonding is also crucial for the bonding of dissimilar materials if the dissimilar materials include materials with low decomposition temperatures or temperature sensitive devices such as, for example, an InP heterojunction bipolar transistor or a processed Si device with ultrashallow source and drain profiles.
The design of processes needed to produce different functions on the same chip containing different materials is difficult and hard to optimize. Indeed, many of the resultant SOC chips (especially those at larger integration size) show a low yield. One approach has been to interconnect fully processed ICs by wafer adhesive bonding and layer transfer. See, for example, Y. Hayashi, S. Wada, K. Kajiyana, K. Oyama, R. Koh, S Takahashi and T. Kunio, Symp. VLSI Tech. Dig. 95 (1990) and U.S. Pat. No. 5,563,084, the entire contents of both references are incorporated herein by reference. However, wafer adhesive bonding usually operates at elevated temperatures and suffers from thermal stress, out-gassing, bubble formation and instability of the adhesive, leading to reduced yield in the process and poor reliability over time. Moreover, the adhesive bond is usually not hermetic.
Wafer direct bonding is a technology that allows wafers to be bonded at room temperature without using any adhesive. The room temperature direct wafer bond is typically hermetic. It is not prone to introduce stress and inhomogeneity as in the adhesive bonding. Further, if the low temperature bonded wafer pairs can withstand a thinning process, when one wafer of a bonded pair is thinned to a thickness less than the respective critical value for the specific materials combination, the generation of misfit dislocations in the layer and sliding or cracking of the bonded pairs during subsequent thermal processing steps can be avoided. See, for example, Q.-Y. Tong and U. Gösele, Semiconductor Wafer Bonding: Science and Technology, John Wiley & Sons, New York, (1999), the entire contents of which are incorporated herein by reference.
Moreover, wafer direct bonding and layer transfer is a VLSI (Very Large Scale Integration) compatible, highly flexible and manufacturable technology, and thus suitable for forming three-dimensional system-on-a chip (3-D SOC). The 3-D SOC approach can be seen as the integration of existing integrated circuits to form a system on a chip.
Moreover, as the integration complexity grows, so do the demands on the integration process to robustly unify diverse circuits at low temperature, preferably at room temperature, resulting in lower or no additional stress and more reliable circuits.
Low or room temperature direct wafer bonding of metal between wafers or dies being bonded is desirable for 3D-SOC preparation. Such direct metal bonding can be used in conjunction with direct wafer bonding of non-metal between wafers or dies to result in electrical interconnection between wafers or dies being bonded when they are mechanically bonded. Simultaneous metal and non-metal bonding can eliminate the need to for post-bond processing, like substrate thinning, via etching, and interconnect metallization, to achieve an electrical interconnection between bonded wafers or die. Very small bonding metal pads can be used, resulting in very low parasitic impedance and resulting reduced power and increased bandwidth capability.
Bonding of metals with clean surfaces is well-known phenomenon. For example, thermocompression wire bonding has been applied to wafer-level bonding. Temperature, pressure and low hardness metals are typically employed and usually results in residual stresses. See, for example, M. A. Schmidt, Proc. IEEE, Vol. 86, No. 8, 1575 (1998), Y. Li, R. W. Bower, I. Bencuya, Jpn. J. Appl. Phys. Vol. 37, L1068 (1988). Direct bonding of Pd metal layer covered silicon or III V compound wafers at 250-350° C. has been reported by B. Aspar, E. Jalaguier, A. Mas, C. Locatelli, O. Rayssac, H. Moricean, S. Pocas, A. Papon, J. Michasud and M. Bruel, Electon. Lett., 35, 12 (1999). However, Pd2Si silicide or Pd-III V alloys, not metal Pd, are actually formed and bonded. Bonding of Au and Al at room temperature has been achieved by using ultrasonic and compressive load at flip chip bonding, see, for example, M. Hizukuri, N. Watanabe and T. Asano, Jpn. J. Appl. Phys. Vol. 40, 3044 (2001). Room temperature metal bonding at wafer level has been realized in ultrahigh vacuum (UHV) systems with a base pressure lower than 3×10−8 mbar. Usually an ion argon sputtering or fast atom-beam is used to clean the bonding surfaces followed by application of an external pressure to the bonding substrates. See, for example, T. Suga, Proc. The 2nd Intl. Symposium on semiconductor wafer bonding, the Electrochemical Soc. Proc. Vol. 93-29, p. 71 (1993). Room temperature bonding between two Si substrates with thin sputtered Ti, Pt and Au films has also been accomplished using applied force after thin film sputter deposition at 4-40 μbar of Ar pressure in a UHV system with base pressure less than 3×10−8 mbar. See, for example, T. Shimatsu, R. H. Mollema, D. Monsma, E. G. Keim and J. C. Lodder, J. Vac. Sci. Technol. A 16(4), 2125 (1998).
Direct bonding of metal features or contacts and non-metal field regions is disclosed in U.S. Pat. No. 7,485,968 and U.S. Pat. No. 6,962,835, the disclosures of each of which are expressly incorporated by reference herein. It can be challenging, however, to achieve both alignment of metal features from two substrates and achieve reliable metal bonding while also directly bonding surrounding non-metal regions.